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Veriloop Coder E1 by tsinghua-sigs-robot-lab

By tsinghua-sigs-robot-lab · 807 downloads

Veriloop Coder E1 is an open-source language model by tsinghua-sigs-robot-lab. Features: 27b LLM, VRAM: 55.6GB, License: apache-2.0, Code Generating, LLM Explorer Score: 0.26.

  Apache-2.0 Base model:finetune:qwen/qwen3...   Base model:qwen/qwen3.6-27b   Code   Codegen   Coding-agent   Conversational   En   Endpoints compatible   Eval-results   Evidence-binding   Harness-engineering   Image-text-to-text   Long-context   Lora   Open-source   Peft   Qwen3 5   Recursive-improvement   Region:us   Repository-understanding   Rollback   Safetensors   Self-harness   Sharded   Software-engineering   Surface-host-adapter   Tensorflow   Tool-use   Uncertainty-calibration   Veriloop   Veriloop-coder   Vertical-code-model   Zh

Veriloop Coder E1 Parameters and Internals

LLM NameVeriloop Coder E1
Repository πŸ€—https://huggingface.co/tsinghua-sigs-robot-lab/veriloop-coder-e1 
Base Model(s)  Qwen/Qwen3.6-27B   Qwen/Qwen3.6-27B
Model Size27b
Required VRAM55.6 GB
Updated2026-08-09
Maintainertsinghua-sigs-robot-lab
Model Typeqwen3_5
Model Files  5.6 GB: 1-of-10   5.7 GB: 2-of-10   5.7 GB: 3-of-10   5.6 GB: 4-of-10   7.5 GB: 5-of-10   5.6 GB: 6-of-10   5.7 GB: 7-of-10   5.7 GB: 8-of-10   5.6 GB: 9-of-10   2.9 GB: 10-of-10
Supported Languagesen zh
Generates CodeYes
Model ArchitectureQwen3_5ForConditionalGeneration
Licenseapache-2.0
Model Max Length262144
Transformers Version4.57.1
Tokenizer ClassQwen2Tokenizer
Padding Token<|endoftext|>
Errorsreplace

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